EP2A25F672C9ES vs EP2A15F672C9 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP2A25F672C9ES disebabkan oleh Intel dan EP2A15F672C9 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Intel
EP2A25F672C9ES EP2A25F672C9ES - APEX II FPGA 900K Gates 236MHz | Intel

EP2A25F672C9ES - APEX II FPGA 900K Gates 236MHz | Intel

EP2A25F672C9ES ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP2A25F672C9ES EP2A15F672C9
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli Obsolete
Family APEX II —
Logic Elements 24,320 16640
System Gates 900,000 —
Maximum Operating Frequency 236 MHz —
Propagation Delay 1.69 ns 1.94 ns
Process Technology 0.15 µm CMOS (up to 8 metal layers, all-layer copper) 0.15 µm all-layer copper (up to 8 metal layers)
Core Supply Voltage 1.5 V 1.5 V
User I/Os 492 —
Kemasan 672-pin FC-FBGA (FineLine BGA), 27 x 27 mm, 1.0 mm pitch 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine)
Speed Grade -9 —
Configuration Class ES (Enhanced) —
Suhu Operasi 0 °C to 85 °C (Commercial) 0 °C to 85 °C (commercial)
Jenis Pemasangan Surface Mount —
Status RoHS [DATA_NEEDED: RoHS compliance status] —
Aras MSL [DATA_NEEDED: MSL moisture sensitivity level] —
Logic Family CMOS APEX II (CMOS)
Usable Gates — 600 K
Macrocells — 1664
Maximum User I/Os — 492
I/O Supply Voltage — 3.3 V
Maximum Internal Frequency — 379 MHz
High-Speed I/O Support — True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps
Embedded Memory — ESB dual-port RAM / FIFO
Configuration Interface — Passive serial / Active serial / JTAG (IEEE 1149.1)
PLLs — On-chip PLLs for clock synthesis and deskew
Compliance — RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan

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