EP2A40F672C6N vs EP2A40F672C8N Comparison
Detailed side-by-side comparison of EP2A40F672C6N by Intel and EP2A40F672C8N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2A40F672C8N
EP2A40F672C8N - APEX II 1.5M Gates FPGA | Intel | 672-BGA
EP2A40F672C8N ObsoleteSpecification Comparison
| Parameter | EP2A40F672C6N | EP2A40F672C8N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $165.00 | $122.00 |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | β |
| Maximum System Gates | 1,125,000 | β |
| Embedded RAM Bits | 442,368 | β |
| Embedded System Blocks (ESBs) | 160 | β |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | β |
| Core Voltage | 1.5 V | β |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | β |
| Package | 672-ball FineLine BGA | β |
| Operating Temperature | Commercial (0C to +85C) | β |
| Speed Grade | C6 (per part number suffix) | C8 |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | β |
| PLL Count | [DATA_NEEDED: PLL count] | β |
| Series | β | EP2A40 |
| Logic Family | β | CMOS |
| System Gates | β | 1.5 M |
| Logic Elements / Cells | β | 38,400 |
| Maximum Operating Frequency | β | 376 MHz |
| Propagation Delay | β | 1.55 ns |
| Technology Node | β | 0.15 Β΅m |
| Process Feature | β | All-layer copper, up to 8 metal layers |
| Nominal Supply Voltage (VCCINT) | β | 1.5 V |
| Supply Voltage Range | β | 1.425 V to 1.575 V |
| User I/Os | β | 492 |
| Number of Pins / Balls | β | 672 |
| Package Type | β | FC-FBGA (FineLine BGA) |
| Package Dimensions | β | 27 x 27 mm |
| Ball Pitch | β | 1.0 mm |
| LVDS Data Rate | β | 1 Gbps |
| Embedded PLLs | β | 4 |
| Programming Interface | β | JTAG (IEEE 1149.1) |
| Operating Temperature (Commercial) | β | 0 Β°C to 85 Β°C |