EP2A70B724I-8 vs EP2A70B724C8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A70B724I-8 sa pamamagitan ng Altera at EP2A70B724C8N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2A70B724C8N - APEX II FPGA, 3M Gates, 724-FCBGA | Altera / Intel
EP2A70B724C8N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2A70B724I-8 | EP2A70B724C8N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | APEX II | FPGA (PLD) |
| Logic Elements / Cells | 67,200 cells | 67,200 |
| System Gates | 3,000,000 | 3,000,000 (3 M) |
| Maximum Internal Frequency | 281 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 um CMOS, SRAM-based |
| Core Supply Voltage | 1.5 V | 1.5 V |
| I/O Supply Voltage | 3.3 V | — |
| Bilang ng Pins | 724 | — |
| Package Type | FCBGA (Flip-Chip Ball Grid Array) | FCBGA-724 (square) |
| Temperature na Operasyon | -40 °C to +100 °C (Industrial) | — |
| Peak Reflow Temperature | 220 °C (per JEDEC J-STD-020) | — |
| User I/O Banks | [DATA_NEEDED: user I/O bank count] | — |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count] | — |
| Embedded RAM | [DATA_NEEDED: total bits] | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| Configuration Method | JTAG / Passive Serial / Passive Parallel | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Series | — | APEX II (EP2A70) |
| Macrocells | — | 16 |
| Product Terms | — | 32 |
| Propagation Delay | — | 2.49 ns |
| Maximum Internal Clock Frequency | — | 281 MHz |
| Maximum Clock Frequency (fMAX) | — | 1694.91 MHz |
| Architecture | — | PLA-type / LUT-based |
| Number of Pins / Balls | — | 724 |
| Terminal Pitch | — | 1.270 mm |
| Maximum User I/O | — | 536 |