EP3SE260H780C4LN vs EP3SE260H780C3N Comparison
Detailed side-by-side comparison of EP3SE260H780C4LN by Intel and EP3SE260H780C3N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP3SE260H780C4LN - Stratix III E FPGA 255K LE 780-FCBGA | Intel
EP3SE260H780C4LN โ Last Time BuyIntel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N โ ActiveSpecification Comparison
| Parameter | EP3SE260H780C4LN | EP3SE260H780C3N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $11,950.00 | $1,325.00 |
| Family | Stratix III E | โ |
| Logic Elements | 255,000 | โ |
| Embedded Memory | 16,672,768 bits (16.67 Mbit) | โ |
| Logic Array Blocks (LABs) | 10,200 | โ |
| Embedded Multipliers (18x18) | 384 | โ |
| User I/O Count | 488 | โ |
| Package | 780-ball FCBGA (FineLine BGA) | 780-BBGA, FCBGA (H780) |
| Speed Grade | C4 (commercial, moderate speed) | โ |
| Operating Temperature | 0C to +85C (commercial) | 0 ยฐC to +85 ยฐC (C grade, commercial) |
| Core Voltage (VCC) | 1.0 V | โ |
| I/O Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) | โ |
| Auxiliary Voltage (VCCPD/VCCPT) | 2.5 V / 3.0 V | โ |
| PLLs | 8 | โ |
| Global Clock Networks | 16 | โ |
| Process Node | 40 nm TSMC | โ |
| Configuration Modes | FPP, AS, PS, JTAG | โ |
| RoHS Status | Compliant | Compliant (lead-free 'N' suffix) |
| MSL Level | 3 (168 hours) | โ |
| Series | โ | Stratixยฎ III E |
| Logic Elements (LE) | โ | 255,000 |
| Embedded Memory (bits) | โ | 16,672,768 |
| Number of LABs/CLBs | โ | 10,200 |
| User I/Os | โ | 488 |
| Number of Pins / Balls | โ | 780 |
| Mounting Type | โ | Surface Mount |
| Process Technology | โ | 40 nm CMOS |
| Maximum Core Frequency | โ | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | โ | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | โ | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | โ | [DATA_NEEDED: number of DSP blocks and precision] |
| Moisture Sensitivity Level (MSL) | โ | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | โ | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | โ | Altera Quartus II (legacy); Intel Quartus Prime |