EP610DC-30 vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610DC-30 by Altera and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β ActiveSpecification Comparison
| Parameter | EP610DC-30 | EP610DC-25 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $9.95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | EP610 (Classic Device Family) | Altera Classic EPLD |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | β |
| Usable Gates | 300 | β |
| Maximum Pipelined Clock Frequency | 100 MHz | β |
| Propagation Delay (tPD) | 30 ns | β |
| Dedicated Inputs | 16 | β |
| I/O Pins | 16 (with output enable) | β |
| Package | 24-pin CERDIP (windowed) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Mounting Type | Through-Hole | Through Hole |
| Speed Grade | -30 (30 ns tPD) | β |
| Technology | CMOS EPROM | CMOS EPROM (UV-erasable) |
| Programmability | UV-erasable, windowed EPROM | β |
| Security Bit | Yes (protects design after programming) | β |
| Output Modes | Registered and Combinatorial | β |
| Operating Temperature | Commercial (0C to +70C) | 0 C to +70 C |
| Equivalent Gates | β | 300 |
| Maximum Propagation Delay (tPD) | β | 25 ns |
| Pipelined Data Rate | β | Up to 100 MHz |
| Number of I/O Pins | β | 22 |
| Number of Dedicated Inputs | β | 4 |
| Total Pin Count | β | 24 |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | β | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | β | -25 (25 ns tPD) |