EP610DC-30 vs EP610DC-25 比較
詳細並排比較 EP610DC-30 由 Altera 與 EP610DC-25 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ 啟用中規格比較
| 參數 | EP610DC-30 | EP610DC-25 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 啟用中 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | EP610 (Classic Device Family) | Altera Classic EPLD |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | — |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | — |
| Dedicated Inputs | 16 | — |
| I/O Pins | 16 (with output enable) | — |
| 封裝 | 24-pin CERDIP (windowed) | 24-pin CDIP (Ceramic DIP, through-hole) |
| 安裝類型 | Through-Hole | Through Hole |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | CMOS EPROM (UV-erasable) |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| 工作溫度 | Commercial (0C to +70C) | 0 C to +70 C |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |