EP610DC-30 vs EP610IDC-10 比較
詳細並排比較 EP610DC-30 由 Altera 與 EP610IDC-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DC-30 | EP610IDC-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 (Classic Device Family) | — |
| Macrocells | 16 | — |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | — |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | — |
| Dedicated Inputs | 16 | 4 |
| I/O Pins | 16 (with output enable) | 20 |
| 封裝 | 24-pin CERDIP (windowed) | — |
| 安裝類型 | Through-Hole | Through-hole |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | CMOS, UV-erasable (windowed ceramic) |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| 工作溫度 | Commercial (0C to +70C) | — |
| Device Family | — | Altera Classic EPLD |
| Logic Capacity | — | 300 usable gates |
| Macrocell Count | — | 16 macrocells |
| Pin-to-Pin Logic Delay (tpd) | — | 10 ns |
| Maximum Counter Frequency (fCNT) | — | 100 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Package Type | — | 24-pin Ceramic DIP (CDIP) |
| 工作溫度範圍 | — | 0 °C to +70 °C (commercial) |
| Programmable Interconnect | — | Yes (on-chip) |
| In-System Programmability | — | Yes (via MAX+PLUS II) |
| Boundary-Scan Test | — | Yes (per device documentation) |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status of CDIP-10 variant] |