EP610DC-30 vs EP610IDC-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-30 sa pamamagitan ng Altera at EP610IDC-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610DC-30 EP610IDC-10
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family EP610 (Classic Device Family) —
Macrocells 16 —
Logic Expanders 4 (4 product terms per macrocell) —
Usable Gates 300 —
Maximum Pipelined Clock Frequency 100 MHz —
Propagation Delay (tPD) 30 ns —
Dedicated Inputs 16 4
I/O Pins 16 (with output enable) 20
Packhaging 24-pin CERDIP (windowed) —
Uri ng Pagpapasok Through-Hole Through-hole
Speed Grade -30 (30 ns tPD) —
Technology CMOS EPROM CMOS, UV-erasable (windowed ceramic)
Programmability UV-erasable, windowed EPROM —
Security Bit Yes (protects design after programming) —
Output Modes Registered and Combinatorial —
Temperature na Operasyon Commercial (0C to +70C) —
Device Family — Altera Classic EPLD
Logic Capacity — 300 usable gates
Macrocell Count — 16 macrocells
Pin-to-Pin Logic Delay (tpd) — 10 ns
Maximum Counter Frequency (fCNT) — 100 MHz
Supply Voltage (VCC) — 5 V (nominal)
I/O Logic Compatibility — 100% TTL emulation
Package Type — 24-pin Ceramic DIP (CDIP)
Hanay ng Temperature na Operasyon — 0 °C to +70 °C (commercial)
Programmable Interconnect — Yes (on-chip)
In-System Programmability — Yes (via MAX+PLUS II)
Boundary-Scan Test — Yes (per device documentation)
Tindminan RoHS — [DATA_NEEDED: RoHS status of CDIP-10 variant]

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