EP610DM-35 vs EP610DC-35 Comparison
Detailed side-by-side comparison of EP610DM-35 by Altera and EP610DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DM-35 | EP610DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $23.40 | $18.40 |
| Manufacturer | Altera (Rochester Electronics authorized stock) | Originally Altera; today supplied via Rochester Electronics (authorized) |
| Part Family | Classic EPLD | β |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | β |
| Number of Macrocells | 16 | β |
| Number of Gates | 300 | β |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Pipelined Data Rate (fMAX) | 100 MHz | β |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| Package | 24-pin CDIP (CERDIP) with UV window | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Temperature Grade (M) | Military -55Β°C to +125Β°C | β |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | β |
| Programmability | UV-erasable, reprogrammable | β |
| Operating Temperature Range | -55Β°C to +125Β°C | β |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| RoHS Status | Non-compliant (contains lead, hermetic CERDIP) | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Device Type | β | CPLD - Classic EPLD |
| Family | β | Altera Classic EP610 |
| Macrocells | β | 16 |
| Usable Gates | β | 300 |
| Maximum Frequency (fMAX) | β | 28.6 MHz |
| Pipelined Data Rate | β | up to 100 MHz |
| Process Technology | β | CMOS |
| Program/erase Method | β | UV-erasable (windowed CERDIP) |
| Mounting Type | β | Through-Hole (DIP) |
| Operating Temperature | β | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |