EP610DM-35 vs EP610DC-35 比較
詳細な並列比較: EP610DM-35 メーカー: Altera および EP610DC-35 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610DM-35 | EP610DC-35 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $23.40 | $18.40 |
| Manufacturer | Altera (Rochester Electronics authorized stock) | Originally Altera; today supplied via Rochester Electronics (authorized) |
| Part Family | Classic EPLD | — |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | — |
| Number of Macrocells | 16 | — |
| Number of Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Pipelined Data Rate (fMAX) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| パッケージ | 24-pin CDIP (CERDIP) with UV window | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Temperature Grade (M) | Military -55°C to +125°C | — |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | — |
| Programmability | UV-erasable, reprogrammable | — |
| 動作温度範囲 | -55°C to +125°C | — |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| RoHS ステータス | Non-compliant (contains lead, hermetic CERDIP) | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Device Type | — | CPLD - Classic EPLD |
| Family | — | Altera Classic EP610 |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| 実装タイプ | — | Through-Hole (DIP) |
| 動作温度 | — | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |