EP610IDC-15 vs EP610DI-30N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610IDC-15 sa pamamagitan ng Intel at EP610DI-30N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610IDC-15 | EP610DI-30N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 15 ns | 30 ns |
| Maximum Frequency | 66 MHz | 33.3 MHz (system); 100 MHz (pipelined) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V ±5% |
| Temperature na Operasyon | 0C to +70C (commercial) | -40°C to +85°C (industrial) |
| Process Technology | CMOS, UV-erasable / OTP | CMOS |
| Packhaging | 24-pin CerDIP (ceramic DIP) | CDIP-24 (Ceramic DIP, windowed) |
| Uri ng Pagpapasok | Through-hole | Through-hole (DIP) |
| I/O Pins | 24 (per package; macrocell-programmable) | — |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status of CerDIP variant] | [DATA_NEEDED: RoHS status] |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EP610 |
| Bilang ng Pin | — | 24 |
| Programming Method | — | UV-erasable (windowed ceramic) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |