EP610IDC-15 vs EP610DI-30N 比較
詳細並排比較 EP610IDC-15 由 Intel 與 EP610DI-30N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610IDC-15 | EP610DI-30N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 15 ns | 30 ns |
| Maximum Frequency | 66 MHz | 33.3 MHz (system); 100 MHz (pipelined) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V ±5% |
| 工作溫度 | 0C to +70C (commercial) | -40°C to +85°C (industrial) |
| Process Technology | CMOS, UV-erasable / OTP | CMOS |
| 封裝 | 24-pin CerDIP (ceramic DIP) | CDIP-24 (Ceramic DIP, windowed) |
| 安裝類型 | Through-hole | Through-hole (DIP) |
| I/O Pins | 24 (per package; macrocell-programmable) | — |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status of CerDIP variant] | [DATA_NEEDED: RoHS status] |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EP610 |
| 腳位數 | — | 24 |
| Programming Method | — | UV-erasable (windowed ceramic) |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |