EP610IPC-10 vs EP610DM-35 Comparison
Detailed side-by-side comparison of EP610IPC-10 by Altera and EP610DM-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IPC-10 | EP610DM-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $23.40 |
| Family | Altera Classic EPLD | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Programmable Gates | 300 usable gates | β |
| Macrocells | 16 | β |
| Maximum Operating Frequency | 100 MHz | β |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | 35 ns |
| Product Terms | 160 total | β |
| Dedicated Inputs | 4 | β |
| I/O Pins | 16 | 24 dedicated I/O (input + bidirectional) |
| Total Input Pins | 20 | β |
| Supply Voltage | 5 V | β |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | β |
| Technology | CMOS EPROM (UV-erasable / OTP) | β |
| Package | 24-pin PDIP (Plastic DIP) | 24-pin CDIP (CERDIP) with UV window |
| Operating Temperature | -40C to +85C (industrial) | β |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | β |
| TTL Emulation | 100% TTL compatible | β |
| Manufacturer | β | Altera (Rochester Electronics authorized stock) |
| Part Family | β | Classic EPLD |
| Logic Family | β | PAL-type EPLD, CMOS, UV-erasable |
| Number of Macrocells | β | 16 |
| Number of Gates | β | 300 |
| Pipelined Data Rate (fMAX) | β | 100 MHz |
| Supply Voltage (VCC) | β | 5 V (single supply) |
| Temperature Grade (M) | β | Military -55Β°C to +125Β°C |
| Programmability | β | UV-erasable, reprogrammable |
| Operating Temperature Range | β | -55Β°C to +125Β°C |
| MSL Level | β | [DATA_NEEDED: MSL rating] |
| RoHS Status | β | Non-compliant (contains lead, hermetic CERDIP) |