EP610IPC-10 vs EP610DM-35 比較
詳細並排比較 EP610IPC-10 由 Altera 與 EP610DM-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610IPC-10 | EP610DM-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Programmable Gates | 300 usable gates | — |
| Macrocells | 16 | — |
| Maximum Operating Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | 35 ns |
| Product Terms | 160 total | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | 24 dedicated I/O (input + bidirectional) |
| Total Input Pins | 20 | — |
| 供應電壓 | 5 V | — |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | — |
| Technology | CMOS EPROM (UV-erasable / OTP) | — |
| 封裝 | 24-pin PDIP (Plastic DIP) | 24-pin CDIP (CERDIP) with UV window |
| 工作溫度 | -40C to +85C (industrial) | — |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | — |
| TTL Emulation | 100% TTL compatible | — |
| Manufacturer | — | Altera (Rochester Electronics authorized stock) |
| Part Family | — | Classic EPLD |
| Logic Family | — | PAL-type EPLD, CMOS, UV-erasable |
| Number of Macrocells | — | 16 |
| Number of Gates | — | 300 |
| Pipelined Data Rate (fMAX) | — | 100 MHz |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Temperature Grade (M) | — | Military -55°C to +125°C |
| Programmability | — | UV-erasable, reprogrammable |
| 工作溫度範圍 | — | -55°C to +125°C |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| RoHS 狀態 | — | Non-compliant (contains lead, hermetic CERDIP) |