EP610JI-30 vs EP610PC-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610JI-30 sa pamamagitan ng Altera at EP610PC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610JI-30 EP610PC-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Family Altera Classic EPLD (EP610) Classic EPLD
Device Type UV Erasable Programmable Logic Device (EPLD) EPLD (Erasable Programmable Logic Device)
Macrocells 16 16
Propagation Delay (tpd) 30 ns (max) —
Pipelined Data Rate Up to 100 MHz Up to 100 MHz
Product Terms 160 —
Dedicated Inputs 4 —
I/O Pins 16 —
External Clocks 2 —
Volte ng Pagbibigay 5 V (single supply) —
Process Technology CMOS —
Packhaging CQCC28 (windowed ceramic JLCC, J-bend) PDIP-24 (plastic DIP, 24-pin)
Package Code JLCC-28 / CQCC28 —
Erasure Method Ultraviolet (UV) via top window —
Programming Altera Logic Programmer compatible —
Temperature na Operasyon -40C to +85C (industrial, per EP610 family suffix convention) [DATA_NEEDED: operating temperature range]
Uri ng Pagpapasok Surface Mount (JLCC) Through-Hole (DIP)
Tindminan RoHS [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Usable Gates — 300 gates
Logic Delay (tPD) — 15 ns (pin-to-pin, -15 speed grade)
Maximum Counter Frequency — 100 MHz (per family datasheet)
Supply Voltage (VCC) — 5 V (single supply)
Technology — CMOS
Architecture — PAL-type, sum-of-products AND/OR array
TTL Emulation — 100% TTL compatible
Bilang ng Pin — 24 pins
Development Tool — Altera MAX+PLUS II
Logic Test Circuitry — On-board for AC/DC verification

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