EP610JI-30 vs EP610PC-15 مقایسه
مقایسه دقیق کنار به کنار EP610JI-30 توسط Altera و EP610PC-15 توسط Altera. مشخصات کلیدی، پارامترهای الکتریکی، بسته‌بندی، وضعیت چرخه عمر، قیمت‌گذاری و موجودی را مقایسه کنید تا بهترین قطعه را برای نیازهای طراحی خود تعیین کنید.
مقایسه مشخصات
| پارامتر | EP610JI-30 | EP610PC-15 |
|---|---|---|
| برند | Altera | Altera |
| دسته‌بندی | FPGA & CPLD | FPGA & CPLD |
| وضعیت چرخه عمر | NRND | NRND |
| Family | Altera Classic EPLD (EP610) | Classic EPLD |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 16 | 16 |
| Propagation Delay (tpd) | 30 ns (max) | — |
| Pipelined Data Rate | Up to 100 MHz | Up to 100 MHz |
| Product Terms | 160 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | — |
| External Clocks | 2 | — |
| ولتاژ تغذیه | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| بسته‌بندی | CQCC28 (windowed ceramic JLCC, J-bend) | PDIP-24 (plastic DIP, 24-pin) |
| Package Code | JLCC-28 / CQCC28 | — |
| Erasure Method | Ultraviolet (UV) via top window | — |
| Programming | Altera Logic Programmer compatible | — |
| دمای کاری | -40C to +85C (industrial, per EP610 family suffix convention) | [DATA_NEEDED: operating temperature range] |
| نوع نصب | Surface Mount (JLCC) | Through-Hole (DIP) |
| وضعیت RoHS | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Usable Gates | — | 300 gates |
| Logic Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | — | 100 MHz (per family datasheet) |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Technology | — | CMOS |
| Architecture | — | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | — | 100% TTL compatible |
| تعداد پایه | — | 24 pins |
| Development Tool | — | Altera MAX+PLUS II |
| Logic Test Circuitry | — | On-board for AC/DC verification |