EP610JI-30 vs EP610PC-15 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610JI-30 disebabkan oleh Altera dan EP610PC-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP610JI-30 EP610PC-15
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND NRND
Family Altera Classic EPLD (EP610) Classic EPLD
Device Type UV Erasable Programmable Logic Device (EPLD) EPLD (Erasable Programmable Logic Device)
Macrocells 16 16
Propagation Delay (tpd) 30 ns (max) —
Pipelined Data Rate Up to 100 MHz Up to 100 MHz
Product Terms 160 —
Dedicated Inputs 4 —
I/O Pins 16 —
External Clocks 2 —
Tegangan Pemberi Arus 5 V (single supply) —
Process Technology CMOS —
Kemasan CQCC28 (windowed ceramic JLCC, J-bend) PDIP-24 (plastic DIP, 24-pin)
Package Code JLCC-28 / CQCC28 —
Erasure Method Ultraviolet (UV) via top window —
Programming Altera Logic Programmer compatible —
Suhu Operasi -40C to +85C (industrial, per EP610 family suffix convention) [DATA_NEEDED: operating temperature range]
Jenis Pemasangan Surface Mount (JLCC) Through-Hole (DIP)
Status RoHS [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Usable Gates — 300 gates
Logic Delay (tPD) — 15 ns (pin-to-pin, -15 speed grade)
Maximum Counter Frequency — 100 MHz (per family datasheet)
Supply Voltage (VCC) — 5 V (single supply)
Technology — CMOS
Architecture — PAL-type, sum-of-products AND/OR array
TTL Emulation — 100% TTL compatible
Kiraan Pin — 24 pins
Development Tool — Altera MAX+PLUS II
Logic Test Circuitry — On-board for AC/DC verification

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