EP610PC-15 vs EP910PC-15 Comparison

Detailed side-by-side comparison of EP610PC-15 by Altera and EP910PC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP910PC-15

EP910PC-15 - 900-Gate Classic EPLD, 15ns PDIP | Altera

EP910PC-15 Obsolete

Specification Comparison

Parameter EP610PC-15 EP910PC-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $17.50 $12.80
Family Classic EPLD Altera Classic EPLD
Device Type EPLD (Erasable Programmable Logic Device) β€”
Usable Gates 300 gates 900
Macrocells 16 24
Logic Delay (tPD) 15 ns (pin-to-pin, -15 speed grade) β€”
Maximum Counter Frequency 100 MHz (per family datasheet) β€”
Pipelined Data Rate Up to 100 MHz β€”
Supply Voltage (VCC) 5 V (single supply) 4.75 V to 5.25 V (5 V nominal)
Technology CMOS β€”
Architecture PAL-type, sum-of-products AND/OR array β€”
TTL Emulation 100% TTL compatible β€”
Package PDIP-24 (plastic DIP, 24-pin) 24-pin PDIP (PDIP-24, 0.300 inch)
Pin Count 24 pins β€”
Operating Temperature [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Mounting Type Through-Hole (DIP) Through-Hole
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - EP910 is a legacy through-hole part, likely non-RoHS]
Development Tool Altera MAX+PLUS II β€”
Logic Test Circuitry On-board for AC/DC verification β€”
Maximum Pin-to-Pin Delay (tpd) β€” 15 ns
Counter Frequency (fCNT) β€” 100 MHz
Supply Current (Icc) β€” 80 mA typical
Dedicated Inputs β€” 10
Dedicated I/O Pins β€” 12
Process Technology β€” CMOS, UV-erasable
Programming Method β€” Altera Logic Programmer card
MSL Level β€” Not applicable (through-hole)

Datasheets & Resources

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