EP610PC-15 vs EP910PC-15 比較
詳細並排比較 EP610PC-15 由 Altera 與 EP910PC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC-15 | EP910PC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 300 gates | 900 |
| Macrocells | 16 | 24 |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS | — |
| Architecture | PAL-type, sum-of-products AND/OR array | — |
| TTL Emulation | 100% TTL compatible | — |
| 封裝 | PDIP-24 (plastic DIP, 24-pin) | 24-pin PDIP (PDIP-24, 0.300 inch) |
| 腳位數 | 24 pins | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| 安裝類型 | Through-Hole (DIP) | Through-Hole |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - EP910 is a legacy through-hole part, likely non-RoHS] |
| Development Tool | Altera MAX+PLUS II | — |
| Logic Test Circuitry | On-board for AC/DC verification | — |
| Maximum Pin-to-Pin Delay (tpd) | — | 15 ns |
| Counter Frequency (fCNT) | — | 100 MHz |
| Supply Current (Icc) | — | 80 mA typical |
| Dedicated Inputs | — | 10 |
| Dedicated I/O Pins | — | 12 |
| Process Technology | — | CMOS, UV-erasable |
| Programming Method | — | Altera Logic Programmer card |
| MSL 等級 | — | Not applicable (through-hole) |