EP9100C-30 vs EP910DI-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP9100C-30 sa pamamagitan ng Altera at EP910DI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP9100C-30 EP910DI-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Aktibo
Family Altera Classic EPLD Altera Classic EPLD
Logic Density 900 usable gates (approx.) —
Macrocells 48 24
Flip-Flops 24 —
Dedicated Inputs 24 10
Propagation Delay (tPD) 30 ns 35 ns
Maximum Toggle Frequency (fMAX) 62.5 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (5 V nominal)
I/O Standard TTL-compatible —
Technology CMOS, UV-erasable (window) or OTP CMOS, UV-erasable EPROM
Temperature na Operasyon 0C to +70C (commercial) -40C to +85C (industrial)
Packhaging 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP CDIP-40 (Ceramic DIP with UV window)
Programming Method JEDEC via Altera APU or compatible programmer EPROM programmer + JEDEC fuse map
Uri ng Pagpapasok Through-Hole (DIP) / Surface Mount (PLCC) Through-Hole
Tindminan RoHS [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified]
Military Grade Variant EP9100C-30/883 (MIL-STD-883 compliant) —
Product Type — EPLD (Erasable Programmable Logic Device)
Usable Gates — 450
Maximum Toggle Frequency (fCNT) — 28.6 MHz
Supply Current (ICC) — 40 mA typical
Bidirectional I/O Pins — 20
Total Pins — 40
Erasure Method — UV light through quartz window
Logic Family — PAL-type AND/OR array with D flip-flops
Manufacturer — Original Altera; long-term authorized by Rochester Electronics, LLC

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