EP9100C-30 vs EP910DI-35 比較
詳細並排比較 EP9100C-30 由 Altera 與 EP910DI-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP9100C-30 | EP910DI-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Logic Density | 900 usable gates (approx.) | — |
| Macrocells | 48 | 24 |
| Flip-Flops | 24 | — |
| Dedicated Inputs | 24 | 10 |
| Propagation Delay (tPD) | 30 ns | 35 ns |
| Maximum Toggle Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Standard | TTL-compatible | — |
| Technology | CMOS, UV-erasable (window) or OTP | CMOS, UV-erasable EPROM |
| 工作溫度 | 0C to +70C (commercial) | -40C to +85C (industrial) |
| 封裝 | 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP | CDIP-40 (Ceramic DIP with UV window) |
| Programming Method | JEDEC via Altera APU or compatible programmer | EPROM programmer + JEDEC fuse map |
| 安裝類型 | Through-Hole (DIP) / Surface Mount (PLCC) | Through-Hole |
| RoHS 狀態 | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] |
| Military Grade Variant | EP9100C-30/883 (MIL-STD-883 compliant) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Maximum Toggle Frequency (fCNT) | — | 28.6 MHz |
| Supply Current (ICC) | — | 40 mA typical |
| Bidirectional I/O Pins | — | 20 |
| Total Pins | — | 40 |
| Erasure Method | — | UV light through quartz window |
| Logic Family | — | PAL-type AND/OR array with D flip-flops |
| Manufacturer | — | Original Altera; long-term authorized by Rochester Electronics, LLC |