EP910DC-30 vs EP910DM-40 比較
詳細並排比較 EP910DC-30 由 Intel 與 EP910DM-40 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910DC-30 | EP910DM-40 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | Altera Classic EP910 |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | PAL-type AND/OR with global programmable interconnect bus |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | 40 ns |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 36 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| 供應電壓 | 5 V | 5 V |
| Process Technology | CMOS | CMOS |
| Programming Method | UV-Erasable / OTP | — |
| 封裝 | DIP-40 (through-hole, 600 mil) | 40-pin Ceramic DIP (Cerdip) with UV window |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| 安裝類型 | Through-Hole | Through-Hole (DIP) |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS compliance status] |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |