EP910DC-30 vs EP910DM-40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DC-30 sa pamamagitan ng Intel at EP910DM-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910DC-30 | EP910DM-40 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | Altera Classic EP910 |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | PAL-type AND/OR with global programmable interconnect bus |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | 40 ns |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 36 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| Volte ng Pagbibigay | 5 V | 5 V |
| Process Technology | CMOS | CMOS |
| Programming Method | UV-Erasable / OTP | — |
| Packhaging | DIP-40 (through-hole, 600 mil) | 40-pin Ceramic DIP (Cerdip) with UV window |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Uri ng Pagpapasok | Through-Hole | Through-Hole (DIP) |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance status] |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |