EP910DC-35 vs EP910IPC-15 Comparison
Detailed side-by-side comparison of EP910DC-35 by Altera and EP910IPC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-35 | EP910IPC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | — |
| Family | Classic EPLD EP910 | — |
| Architecture | PAL-type sum-of-products AND-OR array | PAL-type, CMOS |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | 240 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Clock Frequency | 37 MHz (typical, internal) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | — |
| Operating Temperature | 0 °C to +70 °C (commercial) | 0C to +70C (commercial, IPC suffix) |
| Package | 40-pin CDIP (Ceramic DIP) with quartz window | PDIP-40 (Plastic DIP, 40-pin) |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | JEDEC fuse map via Altera EPLD programmer |
| Technology | CMOS, UV-erasable EPROM cell | — |
| RoHS Status | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: rohs status not confirmed in verified data] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Device Family | — | Altera Classic EPLD (EP910 series) |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| External Clocks | — | 2 |
| Propagation Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Mounting Type | — | Through-Hole |
| Process Technology | — | CMOS |
| Pin Count | — | 40 |