EP910DC-35 vs EP910IPC-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DC-35 sa pamamagitan ng Altera at EP910IPC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DC-35 EP910IPC-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Type UV-Erasable CMOS PLD (PAL-type) —
Family Classic EPLD EP910 —
Architecture PAL-type sum-of-products AND-OR array PAL-type, CMOS
Usable Gates 900 gates —
Macrocells 24 24
Product Terms 240 240
Dedicated Inputs 12 12
I/O Pins 24 24
Total Inputs 36 —
Propagation Delay (tpd) 35 ns —
Maksimum na Taktiko ng Oras 37 MHz (typical, internal) —
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V nominal) —
Temperature na Operasyon 0 °C to +70 °C (commercial) 0C to +70C (commercial, IPC suffix)
Packhaging 40-pin CDIP (Ceramic DIP) with quartz window PDIP-40 (Plastic DIP, 40-pin)
Lead Pitch 2.540 mm —
Termination Style Through-Hole —
Programming Method JEDEC fuse map via device programmer; UV erase JEDEC fuse map via Altera EPLD programmer
Technology CMOS, UV-erasable EPROM cell —
Tindminan RoHS Non-compliant (ceramic DIP with Pb-bearing lead finish) [DATA_NEEDED: rohs status not confirmed in verified data]
Lifecycle Obsolete / last-time-buy from authorized distributors —
Device Family — Altera Classic EPLD (EP910 series)
Product Type — Erasable Programmable Logic Device (EPLD)
External Clocks — 2
Propagation Delay (tPD) — 15 ns
Supply Voltage (VCC) — 4.75 V to 5.25 V
Uri ng Pagpapasok — Through-Hole
Process Technology — CMOS
Bilang ng Pin — 40

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