EP910IDI-15 vs EP910DM-40 Comparison

Detailed side-by-side comparison of EP910IDI-15 by Altera and EP910DM-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910IDI-15 EP910DM-40
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $29.00 $21.00
Family Classic EPLD Altera Classic EP910
Device Type CPLD (Complex Programmable Logic Device) β€”
Logic Gates 450 gates β€”
Macrocells 24 24
Maximum User I/O Pins 36 β€”
Pin-to-Pin Propagation Delay (tpd) 15 ns β€”
Maximum Counter Frequency 66.6 MHz β€”
Supply Voltage (Vcc) 5 V β€”
Technology CMOS EPROM β€”
Program/Erase Method UV-erasable windowed CerDIP β€”
Package 40-pin CDIP (CerDIP) with quartz window 40-pin Ceramic DIP (Cerdip) with UV window
Operating Temperature -40C to +85C (industrial, "I" grade) [DATA_NEEDED: operating temperature range]
Mounting Type Through-hole (DIP) Through-Hole (DIP)
Macrocells Configurable As D, T, JK, SR flip-flop, or combinatorial β€”
Development Tool MAX+PLUS II (legacy) / Altera Classic compiler β€”
Programming Hardware Altera Logic Programmer card β€”
RoHS Status [DATA_NEEDED: RoHS compliance of CDIP windowed part] [DATA_NEEDED: RoHS compliance status]
Logic Family Compatibility Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages β€”
Product Type β€” UV Erasable Programmable Logic Device (EPLD)
Architecture β€” PAL-type AND/OR with global programmable interconnect bus
Dedicated Inputs β€” 36
Dedicated Outputs β€” 24
Bidirectional I/O Lines β€” 24
Product Terms β€” 240
Propagation Delay (tPD) β€” 40 ns
External Clocks β€” 2
Process Technology β€” CMOS
Supply Voltage β€” 5 V
Programming Interface β€” JEDEC-standard fuse-map / UV erasure

Datasheets & Resources

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