EP910IDI-15 vs EP910DM-40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910IDI-15 sa pamamagitan ng Altera at EP910DM-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910IDI-15 | EP910DM-40 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD | Altera Classic EP910 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 gates | — |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 36 | — |
| Pin-to-Pin Propagation Delay (tpd) | 15 ns | — |
| Maximum Counter Frequency | 66.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM | — |
| Program/Erase Method | UV-erasable windowed CerDIP | — |
| Packhaging | 40-pin CDIP (CerDIP) with quartz window | 40-pin Ceramic DIP (Cerdip) with UV window |
| Temperature na Operasyon | -40C to +85C (industrial, "I" grade) | [DATA_NEEDED: operating temperature range] |
| Uri ng Pagpapasok | Through-hole (DIP) | Through-Hole (DIP) |
| Macrocells Configurable As | D, T, JK, SR flip-flop, or combinatorial | — |
| Development Tool | MAX+PLUS II (legacy) / Altera Classic compiler | — |
| Programming Hardware | Altera Logic Programmer card | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance of CDIP windowed part] | [DATA_NEEDED: RoHS compliance status] |
| Logic Family Compatibility | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages | — |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Dedicated Inputs | — | 36 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 40 ns |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| Volte ng Pagbibigay | — | 5 V |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |