EP910IDI-15 vs EP910DM-40 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910IDI-15 disebabkan oleh Altera dan EP910DM-40 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP910IDI-15 EP910DM-40
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Classic EPLD Altera Classic EP910
Device Type CPLD (Complex Programmable Logic Device) —
Logic Gates 450 gates —
Macrocells 24 24
Maximum User I/O Pins 36 —
Pin-to-Pin Propagation Delay (tpd) 15 ns —
Maximum Counter Frequency 66.6 MHz —
Supply Voltage (Vcc) 5 V —
Technology CMOS EPROM —
Program/Erase Method UV-erasable windowed CerDIP —
Kemasan 40-pin CDIP (CerDIP) with quartz window 40-pin Ceramic DIP (Cerdip) with UV window
Suhu Operasi -40C to +85C (industrial, "I" grade) [DATA_NEEDED: operating temperature range]
Jenis Pemasangan Through-hole (DIP) Through-Hole (DIP)
Macrocells Configurable As D, T, JK, SR flip-flop, or combinatorial —
Development Tool MAX+PLUS II (legacy) / Altera Classic compiler —
Programming Hardware Altera Logic Programmer card —
Status RoHS [DATA_NEEDED: RoHS compliance of CDIP windowed part] [DATA_NEEDED: RoHS compliance status]
Logic Family Compatibility Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages —
Product Type — UV Erasable Programmable Logic Device (EPLD)
Architecture — PAL-type AND/OR with global programmable interconnect bus
Dedicated Inputs — 36
Dedicated Outputs — 24
Bidirectional I/O Lines — 24
Product Terms — 240
Propagation Delay (tPD) — 40 ns
External Clocks — 2
Process Technology — CMOS
Tegangan Pemberi Arus — 5 V
Programming Interface — JEDEC-standard fuse-map / UV erasure

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