EP910IDI-15 vs EP910DM-40 对比
详细并排对比 EP910IDI-15 出自 Altera 和 EP910DM-40 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910IDI-15 | EP910DM-40 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $29.00 | $21.00 |
| Family | Classic EPLD | Altera Classic EP910 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 gates | — |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 36 | — |
| Pin-to-Pin Propagation Delay (tpd) | 15 ns | — |
| Maximum Counter Frequency | 66.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM | — |
| Program/Erase Method | UV-erasable windowed CerDIP | — |
| 封装 | 40-pin CDIP (CerDIP) with quartz window | 40-pin Ceramic DIP (Cerdip) with UV window |
| 工作温度 | -40C to +85C (industrial, "I" grade) | [DATA_NEEDED: operating temperature range] |
| 安装类型 | Through-hole (DIP) | Through-Hole (DIP) |
| Macrocells Configurable As | D, T, JK, SR flip-flop, or combinatorial | — |
| Development Tool | MAX+PLUS II (legacy) / Altera Classic compiler | — |
| Programming Hardware | Altera Logic Programmer card | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance of CDIP windowed part] | [DATA_NEEDED: RoHS compliance status] |
| Logic Family Compatibility | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages | — |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Dedicated Inputs | — | 36 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 40 ns |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| 电源电压 | — | 5 V |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |