EP910ILC-25 vs EP910DM-40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-25 sa pamamagitan ng Intel at EP910DM-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910ILC-25 | EP910DM-40 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | EP910 Classic EPLD | Altera Classic EP910 |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 25 ns | 40 ns |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| Packhaging | 44-pin JLCC (windowed ceramic) | 40-pin Ceramic DIP (Cerdip) with UV window |
| Uri ng Pagpapasok | Surface Mount | Through-Hole (DIP) |
| Temperature na Operasyon | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Volte ng Pagbibigay | 5 V | 5 V |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Tindminan RoHS | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS compliance status] |
| Katayuan ng Lifecycle | Obsolete - last time buy was late 1990s | — |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Dedicated Inputs | — | 36 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |