EP910ILC-25 vs EP910DM-40 比較
詳細並排比較 EP910ILC-25 由 Intel 與 EP910DM-40 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910ILC-25 | EP910DM-40 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | EP910 Classic EPLD | Altera Classic EP910 |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 25 ns | 40 ns |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| 封裝 | 44-pin JLCC (windowed ceramic) | 40-pin Ceramic DIP (Cerdip) with UV window |
| 安裝類型 | Surface Mount | Through-Hole (DIP) |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| 供應電壓 | 5 V | 5 V |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS 狀態 | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS compliance status] |
| 生命週期狀態 | Obsolete - last time buy was late 1990s | — |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Dedicated Inputs | — | 36 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |