EP910LC-32 vs EP910LC-35 Comparison
Detailed side-by-side comparison of EP910LC-32 by Altera and EP910LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-32 | EP910LC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | 900 gates (typical) | — |
| Number of Dedicated Inputs | 10 | — |
| Number of I/O Pins | 20 | — |
| Package | PLCC-32 | PLCC-44 (J-lead, LC suffix) |
| Speed Grade | -32 | — |
| Maximum Toggle Frequency (fMAX) | [DATA_NEEDED: fMAX value in MHz for -32 grade] | — |
| Pin-to-Pin Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns for -32 grade] | — |
| Supply Voltage (VCC) | 5 V | 5 V |
| Logic Family | Low-power CMOS (LC suffix) | — |
| Programming Method | UV-erasable or one-time programmable (OTP for LC windowless variant) | — |
| Operating Temperature Range | [DATA_NEEDED: commercial or industrial grade] | — |
| I/O Standard | TTL-compatible | — |
| Mounting Type | Surface Mount (PLCC socket or direct solder) | — |
| RoHS Status | unknown | Not applicable (legacy product) |
| MSL Level | unknown | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic (EP910) |
| Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Technology | — | CMOS EPROM |
| Operating Temperature | — | 0C to +70C (commercial) |
| Pin Count | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |