EP910LC-35H vs EP910DM-40 Comparison

Detailed side-by-side comparison of EP910LC-35H by Altera and EP910DM-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910LC-35H EP910DM-40
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $25.00 $21.00
Family Classic EPLD (EP910) Altera Classic EP910
Logic Elements 24 macrocells β€”
Equivalent Gates 450 usable gates β€”
Propagation Delay (tpd) 35 ns β€”
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) β€”
Technology CMOS, UV-erasable EPROM β€”
Package 40-pin Ceramic DIP (H suffix) 40-pin Ceramic DIP (Cerdip) with UV window
User I/O Pins 36 β€”
Dedicated Inputs 10 36
Operating Temperature [DATA_NEEDED: operating temperature range grade] [DATA_NEEDED: operating temperature range]
Erasure Method UV (quartz window on H package) β€”
Programming Method Altera hardware programmer β€”
Logic Levels TTL compatible β€”
Quiescent Current [DATA_NEEDED: typical ICC value] β€”
Process Node [DATA_NEEDED: process geometry] β€”
Mounting Type Through-hole (Ceramic DIP) Through-Hole (DIP)
RoHS Status unknown [DATA_NEEDED: RoHS compliance status]
Lifecycle Obsolete (long-term supply via Rochester Electronics) β€”
Product Type β€” UV Erasable Programmable Logic Device (EPLD)
Architecture β€” PAL-type AND/OR with global programmable interconnect bus
Macrocells β€” 24
Dedicated Outputs β€” 24
Bidirectional I/O Lines β€” 24
Product Terms β€” 240
Propagation Delay (tPD) β€” 40 ns
External Clocks β€” 2
Process Technology β€” CMOS
Supply Voltage β€” 5 V
Programming Interface β€” JEDEC-standard fuse-map / UV erasure

Datasheets & Resources

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