EP910LC-35H vs EP910DM-40 Vergleich

Detaillierter Direktvergleich von EP910LC-35H von Altera und EP910DM-40 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910LC-35H EP910DM-40
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $25,00 $21,00
Family Classic EPLD (EP910) Altera Classic EP910
Logic Elements 24 macrocells —
Equivalent Gates 450 usable gates —
Propagation Delay (tpd) 35 ns —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Technology CMOS, UV-erasable EPROM —
Gehäuse 40-pin Ceramic DIP (H suffix) 40-pin Ceramic DIP (Cerdip) with UV window
User I/O Pins 36 —
Dedicated Inputs 10 36
Betriebstemperatur [DATA_NEEDED: operating temperature range grade] [DATA_NEEDED: operating temperature range]
Erasure Method UV (quartz window on H package) —
Programming Method Altera hardware programmer —
Logic Levels TTL compatible —
Ruhestrom [DATA_NEEDED: typical ICC value] —
Process Node [DATA_NEEDED: process geometry] —
Montageart Through-hole (Ceramic DIP) Through-Hole (DIP)
RoHS-Status unknown [DATA_NEEDED: RoHS compliance status]
Lifecycle Obsolete (long-term supply via Rochester Electronics) —
Product Type — UV Erasable Programmable Logic Device (EPLD)
Architecture — PAL-type AND/OR with global programmable interconnect bus
Macrocells — 24
Dedicated Outputs — 24
Bidirectional I/O Lines — 24
Product Terms — 240
Propagation Delay (tPD) — 40 ns
External Clocks — 2
Process Technology — CMOS
Versorgungsspannung — 5 V
Programming Interface — JEDEC-standard fuse-map / UV erasure

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