EP910LC-35H vs EP910DM-40 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-35H sa pamamagitan ng Altera at EP910DM-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910LC-35H EP910DM-40
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Classic EPLD (EP910) Altera Classic EP910
Logic Elements 24 macrocells —
Equivalent Gates 450 usable gates —
Propagation Delay (tpd) 35 ns —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Technology CMOS, UV-erasable EPROM —
Packhaging 40-pin Ceramic DIP (H suffix) 40-pin Ceramic DIP (Cerdip) with UV window
User I/O Pins 36 —
Dedicated Inputs 10 36
Temperature na Operasyon [DATA_NEEDED: operating temperature range grade] [DATA_NEEDED: operating temperature range]
Erasure Method UV (quartz window on H package) —
Programming Method Altera hardware programmer —
Logic Levels TTL compatible —
Kuru-kuryente ng Kapayapaan [DATA_NEEDED: typical ICC value] —
Process Node [DATA_NEEDED: process geometry] —
Uri ng Pagpapasok Through-hole (Ceramic DIP) Through-Hole (DIP)
Tindminan RoHS unknown [DATA_NEEDED: RoHS compliance status]
Lifecycle Obsolete (long-term supply via Rochester Electronics) —
Product Type — UV Erasable Programmable Logic Device (EPLD)
Architecture — PAL-type AND/OR with global programmable interconnect bus
Macrocells — 24
Dedicated Outputs — 24
Bidirectional I/O Lines — 24
Product Terms — 240
Propagation Delay (tPD) — 40 ns
External Clocks — 2
Process Technology — CMOS
Volte ng Pagbibigay — 5 V
Programming Interface — JEDEC-standard fuse-map / UV erasure

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