EP910LI-40T vs EP910LI-35 Comparison
Detailed side-by-side comparison of EP910LI-40T by Intel and EP910LI-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-40T | EP910LI-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Supply Voltage | 5 V (typical) | 5 V (4.75 V to 5.25 V) |
| Operating Temperature | -40C to +85C (Industrial) | -40 °C to +85 °C (Industrial) |
| Architecture | PAL-type with global bus | — |
| Package | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | 44-pin PLCC (J-lead) |
| RoHS Status | [DATA_NEEDED: rohs status] | — |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | — |
| Device Series | — | EP910 |
| Usable Gates | — | 900 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Mounting Type | — | Surface Mount |
| Lead Pitch | — | 1.27 mm |