EP910LI-40T vs EP910LI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-40T sa pamamagitan ng Intel at EP910LI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-40T | EP910LI-35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Volte ng Pagbibigay | 5 V (typical) | 5 V (4.75 V to 5.25 V) |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40 °C to +85 °C (Industrial) |
| Architecture | PAL-type with global bus | — |
| Packhaging | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | 44-pin PLCC (J-lead) |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | — |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | — |
| Device Series | — | EP910 |
| Usable Gates | — | 900 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Uri ng Pagpapasok | — | Surface Mount |
| Lead Pitch | — | 1.27 mm |