EP910LI-40T vs EP910LI-35 比較
詳細並排比較 EP910LI-40T 由 Intel 與 EP910LI-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-40T | EP910LI-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Technology | CMOS, UV-erasable EPROM | — |
| 供應電壓 | 5 V (typical) | 5 V (4.75 V to 5.25 V) |
| 工作溫度 | -40C to +85C (Industrial) | -40 °C to +85 °C (Industrial) |
| Architecture | PAL-type with global bus | — |
| 封裝 | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | 44-pin PLCC (J-lead) |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | — |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | — |
| Device Series | — | EP910 |
| Usable Gates | — | 900 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| 安裝類型 | — | Surface Mount |
| Lead Pitch | — | 1.27 mm |