EP910LI-40T vs EP910LI-40 比較
詳細並排比較 EP910LI-40T 由 Intel 與 EP910LI-40 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-40T | EP910LI-40 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 bidirectional |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Technology | CMOS, UV-erasable EPROM | Low-power CMOS (L-suffix) |
| 供應電壓 | 5 V (typical) | — |
| 工作溫度 | -40C to +85C (Industrial) | -40C to +85C (industrial, I-suffix) |
| Architecture | PAL-type with global bus | — |
| 封裝 | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | PLCC-44 (J-lead, windowed ceramic) |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | Non-compliant (windowed ceramic PLCC, legacy) |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Product Family | — | Classic EPLD - EP910 series |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Maximum Logic Inputs | — | 36 |
| 安裝類型 | — | Surface Mount (socket-compatible) |
| Programmability | — | UV-erasable, JEDEC-standard algorithm |
| Lifecycle | — | Obsolete - replaced by MAX 7000 / MAX II CPLD family |