EP910LI-40T vs EP910LI-40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-40T sa pamamagitan ng Intel at EP910LI-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-40T | EP910LI-40 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Classic EPLD | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 bidirectional |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Technology | CMOS, UV-erasable EPROM | Low-power CMOS (L-suffix) |
| Volte ng Pagbibigay | 5 V (typical) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40C to +85C (industrial, I-suffix) |
| Architecture | PAL-type with global bus | — |
| Packhaging | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | PLCC-44 (J-lead, windowed ceramic) |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Non-compliant (windowed ceramic PLCC, legacy) |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Product Family | — | Classic EPLD - EP910 series |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Maximum Logic Inputs | — | 36 |
| Uri ng Pagpapasok | — | Surface Mount (socket-compatible) |
| Programmability | — | UV-erasable, JEDEC-standard algorithm |
| Lifecycle | — | Obsolete - replaced by MAX 7000 / MAX II CPLD family |