EP910PC-35 vs EP910PC30T Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-35 sa pamamagitan ng Altera at EP910PC30T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910PC-35 EP910PC30T
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Classic EPLD Altera Classic EPLD
Device Type EPLD (Erasable Programmable Logic Device) —
Macrocells 24 —
I/O Pins 24 —
Dedicated Inputs 12 —
Total Inputs 36 —
Product Terms 240 —
Propagation Delay (tPD) 35 ns 30 ns
Maximum Counter Frequency 37 MHz —
Internal Performance Frequency 100 MHz —
Technology CMOS, UV-erasable/OTP —
Volte ng Pagbibigay 5 V —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Packhaging 40-pin PDIP (Plastic DIP) 24-pin PDIP (PC)
Uri ng Pagpapasok Through-Hole Through-Hole (THT)
Architecture PAL-type sum-of-products, AND/OR array —
Programming Method UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools —
Compliance / RoHS [DATA_NEEDED: RoHS status - legacy part] —
Device Series — EP910
Number of Macrocells — 24
Number of I/O Pins — 24
Number of Dedicated Inputs — 12
Maximum Product Terms — 240
Maximum Clock Frequency (fMAX) — 33.3 MHz
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Process Technology — CMOS
Programmable Logic Architecture — PAL-type sum-of-products, EPLD
Speed Grade — -30 (30 ns tPD)
Programming Technology — EPROM (OTP in plastic package, UV-erasable in windowed package)
Tindminan RoHS — [DATA_NEEDED: RoHS compliance status]
Bilang ng Pin — 24

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