EP910PI-20T vs EP910PI-12T 比較
詳細な並列比較: EP910PI-20T メーカー: Intel および EP910PI-12T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910PI-20T | EP910PI-12T |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $9.95 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | — |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | [DATA_NEEDED: usable gate count] | — |
| Propagation Delay (tpd) | 20 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Pins | 20 | — |
| ピン数 | 40 | — |
| パッケージ | PDIP-40 (PI) | 40-pin PDIP (Plastic DIP) |
| 実装タイプ | Through-Hole (DIP) | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Programming | Standard EPROM programmer, JEDEC map | — |
| RoHS ステータス | unknown | Non-compliant (legacy PDIP package, contains lead) |
| ライフサイクル状態 | Not Recommended for New Designs (NRND) | NRND / EOL (mature legacy product) |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 12 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Logic Gates | — | [DATA_NEEDED: logic gate count] |
| Supply Voltage (VCC) | — | 5 V (4.75 V min, 5.25 V max) |
| I/O Pins | — | 24 |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 2 |
| Outputs | — | 24 |
| Terminals / Pin Count | — | 44 (PDIP-40 package pinout with NC pins) |
| Process Technology | — | CMOS |
| Programmable Technology | — | UV-erasable EPROM |
| Programming Interface | — | JEDEC-standard |