EP910PI-20T vs EP910PI-20 比較
詳細並排比較 EP910PI-20T 由 Intel 與 EP910PI-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PI-20T | EP910PI-20 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Altera Classic EPLD | — |
| Device | EP910 | — |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | [DATA_NEEDED: usable gate count] | — |
| Propagation Delay (tpd) | 20 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Pins | 20 | — |
| 腳位數 | 40 | — |
| 封裝 | PDIP-40 (PI) | PDIP-40 (PI suffix) |
| 安裝類型 | Through-Hole (DIP) | Through-Hole |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM (UV-erasable windowed variants available) |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Programming | Standard EPROM programmer, JEDEC map | — |
| RoHS 狀態 | unknown | unknown |
| 生命週期狀態 | Not Recommended for New Designs (NRND) | — |
| Device Family | — | Altera Classic EPLD Family |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5 V (+/- 5%) |
| Configuration Method | — | Non-volatile EPROM (no boot PROM required) |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 24 |
| Maximum Counter Frequency | — | 125 MHz |
| Output Drive Current (IOL) | — | 24 mA (TTL-compatible) |
| Programmable Polarity | — | Yes (XOR gate per macrocell) |
| Macrocell Flip-Flop | — | Yes (D-type, programmable) |
| Power Dissipation | — | [DATA_NEEDED: typical power dissipation in mW] |
| Programming Interface | — | JEDEC file via Altera programming hardware |
| MIL-STD-883 Variant | — | EP910DM/883B (separate part number) |