EP910PI-20T vs EP910PI-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-20T sa pamamagitan ng Intel at EP910PI-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910PI-20T EP910PI-20
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family Altera Classic EPLD —
Device EP910 —
Number of Macrocells 24 —
Number of Usable Gates [DATA_NEEDED: usable gate count] —
Propagation Delay (tpd) 20 ns —
Maximum Toggle Frequency 62.5 MHz —
Number of Dedicated Inputs 12 —
Number of I/O Pins 20 —
Bilang ng Pins 40 —
Packhaging PDIP-40 (PI) PDIP-40 (PI suffix)
Uri ng Pagpapasok Through-Hole (DIP) Through-Hole
Technology CMOS EPROM (UV-erasable) CMOS EPROM (UV-erasable windowed variants available)
Temperature na Operasyon [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
Programming Standard EPROM programmer, JEDEC map —
Tindminan RoHS unknown unknown
Katayuan ng Lifecycle Not Recommended for New Designs (NRND) —
Device Family — Altera Classic EPLD Family
Macrocells — 24
Propagation Delay (tPD) — 20 ns
Supply Voltage (VCC) — 5 V (+/- 5%)
Configuration Method — Non-volatile EPROM (no boot PROM required)
Dedicated Inputs — 12
Bidirectional I/O Pins — 24
Maximum Counter Frequency — 125 MHz
Output Drive Current (IOL) — 24 mA (TTL-compatible)
Programmable Polarity — Yes (XOR gate per macrocell)
Macrocell Flip-Flop — Yes (D-type, programmable)
Power Dissipation — [DATA_NEEDED: typical power dissipation in mW]
Programming Interface — JEDEC file via Altera programming hardware
MIL-STD-883 Variant — EP910DM/883B (separate part number)

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