EPC1L20 vs EPC1LI20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC1L20 sa pamamagitan ng Altera at EPC1LI20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC1L20 | EPC1LI20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Uri ng Memory | OTP Configuration PROM (Flash) | OTP Configuration PROM (EPROM-based) |
| Laki ng Memory | 1 Mbit | 1 Mb (1,048,576 bits) |
| Configuration Clock (max) | 8 MHz | — |
| Flash Access Time | 90 ns (approx.) | — |
| Max Read Bandwidth | 160 Mbps (16-bit DQ bus) | — |
| Interface | Serial / FPP configuration + JTAG (IEEE 1149.1) | — |
| Volte ng Pagbibigay | 3.3 V (typical) | — |
| Programmability | One-Time Programmable (OTP) | — |
| Packhaging | 20-pin PLCC (9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Uri ng Pagpapasok | Through-Hole / Socket | Surface Mount (PLCC socket compatible) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| JTAG / ISP Support | Yes (IEEE 1149.1) | — |
| Compatible FPGA Series | Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Interface | — | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) |
| Maximum Configuration Clock | — | 8 MHz |
| Supply Voltage (VCC) | — | 5.0 V (4.75 V to 5.25 V) |
| Programming Voltage (VPP) | — | 12.75 V (typical, factory-programmed via JTAG) |
| Bilang ng Pin | — | 20 |
| Cascading Support | — | Yes (nCASC pin for multi-device daisy chain) |
| Endurance | — | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) |
| JTAG Programming | — | Yes (in-system via IEEE 1149.1) |
| Compatible FPGA Families | — | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury |
| Level ng MSL | — | 1 (per Partstack datasheet record) |