EPC1L20 vs EPC1LI20 比較
詳細並排比較 EPC1L20 由 Altera 與 EPC1LI20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC1L20 | EPC1LI20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | 啟用中 | Obsolete |
| 記憶體類型 | OTP Configuration PROM (Flash) | OTP Configuration PROM (EPROM-based) |
| 記憶體容量 | 1 Mbit | 1 Mb (1,048,576 bits) |
| Configuration Clock (max) | 8 MHz | — |
| Flash Access Time | 90 ns (approx.) | — |
| Max Read Bandwidth | 160 Mbps (16-bit DQ bus) | — |
| 介面 | Serial / FPP configuration + JTAG (IEEE 1149.1) | — |
| 供應電壓 | 3.3 V (typical) | — |
| Programmability | One-Time Programmable (OTP) | — |
| 封裝 | 20-pin PLCC (9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| 安裝類型 | Through-Hole / Socket | Surface Mount (PLCC socket compatible) |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| JTAG / ISP Support | Yes (IEEE 1149.1) | — |
| Compatible FPGA Series | Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Interface | — | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) |
| Maximum Configuration Clock | — | 8 MHz |
| Supply Voltage (VCC) | — | 5.0 V (4.75 V to 5.25 V) |
| Programming Voltage (VPP) | — | 12.75 V (typical, factory-programmed via JTAG) |
| 腳位數 | — | 20 |
| Cascading Support | — | Yes (nCASC pin for multi-device daisy chain) |
| Endurance | — | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) |
| JTAG Programming | — | Yes (in-system via IEEE 1149.1) |
| Compatible FPGA Families | — | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury |
| MSL 等級 | — | 1 (per Partstack datasheet record) |