EPC2LC20-U vs EPC2LI20 Comparison

Detailed side-by-side comparison of EPC2LC20-U by Altera and EPC2LI20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC2LC20-U EPC2LI20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete NRND
Memory Type Configuration PROM (Flash, in-system programmable) Flash (in-system programmable)
Memory Size 1.6 Mbit 1.6 Mb (1,572,864 bits)
Interface Serial (4-wire Altera configuration) + JTAG (IEEE 1149.1) —
Max Configuration Clock 10 MHz —
Supply Voltage (VCC) 3.3 V (3.0 V to 3.6 V) —
Programmable In-system via JTAG —
Cascade Support Yes (multi-PROM for larger bitstreams) —
Package 20-PLCC (9x9) —
Mounting Type Surface Mount Surface Mount (PLCC socket-compatible)
Operating Temperature [DATA_NEEDED: full operating temperature range] -40 C to +85 C (Industrial)
Supported FPGA Families ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K —
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
MSL Level [DATA_NEEDED: moisture sensitivity level] [DATA_NEEDED: MSL level]
Programmable Type — In System Programmable (ISP)
Function — Configuration PROM for SRAM-based FPGAs
Supply Voltage - Operating — 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing)
Package / Case — 20-PLCC (J-lead, 9x9 mm)
Configuration Interface — Serial or Byte-wide (parallel)
Decompression — On-chip (supports compressed bitstreams)
JTAG / ISP Interface — IEEE 1532 (TCK, TMS, TDI, TDO)
Multi-Device Support — Yes (daisy-chain configuration)
User-Accessible Memory — Yes (unused flash available to user logic)

Datasheets & Resources

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