EPC2LC20-U vs EPC2LI20 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPC2LC20-U disebabkan oleh Altera dan EPC2LI20 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPC2LC20-U EPC2LI20
Merek Altera Altera
Kategori Memory ICs Memory ICs
Status Lingkungan Hidup Obsolete NRND
Jenis Ingatan Configuration PROM (Flash, in-system programmable) Flash (in-system programmable)
Saiz Ingatan 1.6 Mbit 1.6 Mb (1,572,864 bits)
Antaramuka Serial (4-wire Altera configuration) + JTAG (IEEE 1149.1) —
Max Configuration Clock 10 MHz —
Supply Voltage (VCC) 3.3 V (3.0 V to 3.6 V) —
Programmable In-system via JTAG —
Cascade Support Yes (multi-PROM for larger bitstreams) —
Kemasan 20-PLCC (9x9) —
Jenis Pemasangan Surface Mount Surface Mount (PLCC socket-compatible)
Suhu Operasi [DATA_NEEDED: full operating temperature range] -40 C to +85 C (Industrial)
Supported FPGA Families ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K —
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
Status RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Aras MSL [DATA_NEEDED: moisture sensitivity level] [DATA_NEEDED: MSL level]
Programmable Type — In System Programmable (ISP)
Fungsi — Configuration PROM for SRAM-based FPGAs
Supply Voltage - Operating — 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing)
Kemasan / Case — 20-PLCC (J-lead, 9x9 mm)
Configuration Interface — Serial or Byte-wide (parallel)
Decompression — On-chip (supports compressed bitstreams)
JTAG / ISP Interface — IEEE 1532 (TCK, TMS, TDI, TDO)
Multi-Device Support — Yes (daisy-chain configuration)
User-Accessible Memory — Yes (unused flash available to user logic)

Laporan Datasheet & Sumber

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