EPC2LC20N-W vs EPC2LC20NU Comparison

Detailed side-by-side comparison of EPC2LC20N-W by Altera and EPC2LC20NU by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC2LC20N-W EPC2LC20NU
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $6.45 $8.20
Memory Type EPROM (UV-erasable, ISP) β€”
Memory Size 1.6 Mbit β€”
Programmable Type In System Programmable β€”
Configuration Interface Serial (DATA, DCLK, OE, nCS) β€”
Internal Oscillator Frequency 66.7 MHz β€”
Supply Voltage (VCC) 3.0 V to 3.6 V, 4.75 V to 5.25 V 3.0 V to 3.6 V
ISP Interface JTAG (IEEE 1149.1) β€”
Supported FPGA Families APEX 20K, ACEX 1K, Mercury, FLEX 10K, Stratix, Cyclone β€”
Package 20-LCC (J-Lead) PLCC-20 20-pin J-lead PLCC (9x9 mm)
Mounting Type Surface Mount Surface Mount
Packaging Tape & Reel (-W suffix) β€”
Cascade Support Yes (with other EPC2 devices) Yes - daisy-chain for larger bitstreams
Pin Count 20 β€”
Lead-Free / RoHS [DATA_NEEDED: RoHS status for -W variant] Non-LEAD / non-RoHS (NU suffix = matte tin Sn finish, not Pb-free)
Operating Temperature [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Function β€” In-System Programmable Configuration PROM
Memory Density β€” 1.6 Mbit
FPGA Interface β€” Altera serial (4-pin: nCS, DCLK, DATA, nINIT_CONF)
I/O Tolerance β€” 5 V tolerant inputs (per datasheet, except JTAG pins)
Programming Method β€” In-system via IEEE 1149.1 JTAG
JTAG Support β€” Yes (IEEE Std 1149.1 boundary-scan compliant)
Minimum DC Input β€” -0.3 V (inputs may undershoot to -2.0 V for <20 ns)
Maximum Overshoot β€” 7.0 V for <100 mA and <20 ns
Compatibility β€” Altera APEX 20K, APEX II, Mercury, FLEX 10K, ACEX 1K, Cyclone (legacy serial configuration)

Datasheets & Resources

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