EPC2LC20N-W vs EPC2LC20NU 对比

详细并排对比 EPC2LC20N-W 出自 Altera 和 EPC2LC20NU 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC2LC20N-W EPC2LC20NU
品牌 Altera Altera
分类 Memory ICs Memory ICs
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $6.45 $8.20
存储器类型 EPROM (UV-erasable, ISP) —
存储容量 1.6 Mbit —
Programmable Type In System Programmable —
Configuration Interface Serial (DATA, DCLK, OE, nCS) —
Internal Oscillator Frequency 66.7 MHz —
Supply Voltage (VCC) 3.0 V to 3.6 V, 4.75 V to 5.25 V 3.0 V to 3.6 V
ISP Interface JTAG (IEEE 1149.1) —
Supported FPGA Families APEX 20K, ACEX 1K, Mercury, FLEX 10K, Stratix, Cyclone —
封装 20-LCC (J-Lead) PLCC-20 20-pin J-lead PLCC (9x9 mm)
安装类型 Surface Mount Surface Mount
Packaging Tape & Reel (-W suffix) —
Cascade Support Yes (with other EPC2 devices) Yes - daisy-chain for larger bitstreams
引脚数量 20 —
Lead-Free / RoHS [DATA_NEEDED: RoHS status for -W variant] Non-LEAD / non-RoHS (NU suffix = matte tin Sn finish, not Pb-free)
工作温度 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
功能 — In-System Programmable Configuration PROM
Memory Density — 1.6 Mbit
FPGA Interface — Altera serial (4-pin: nCS, DCLK, DATA, nINIT_CONF)
I/O Tolerance — 5 V tolerant inputs (per datasheet, except JTAG pins)
Programming Method — In-system via IEEE 1149.1 JTAG
JTAG Support — Yes (IEEE Std 1149.1 boundary-scan compliant)
Minimum DC Input — -0.3 V (inputs may undershoot to -2.0 V for <20 ns)
Maximum Overshoot — 7.0 V for <100 mA and <20 ns
Compatibility — Altera APEX 20K, APEX II, Mercury, FLEX 10K, ACEX 1K, Cyclone (legacy serial configuration)

数据手册与资源

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